模数/数模转换器(AD/DA)
研究方向一：高速高精度TI/single-channel pipelined ADC
主要研究采样率100MHz-10GHz、精度10-16bit的pipelined ADC、multibit/cycle SAR ADC等。
代表性成果：
研究方向二：高速低功耗SAR/NS-SAR ADC
主要研究采样率50MHz-500MHz、带宽20MHz-250MHz、功耗mW-level的SAR、NS-SAR ADC。
代表性成果：
研究方向三：低通/带通-宽带sigma-delta ADC
主要研究带宽20MHz以上的低通、带通sigma-delta ADC/SDM。
代表性成果：
研究方向四：高精度SAR/NS-SAR ADC
主要研究奈奎斯特采样率1MHz以上、SNDR>84dB的高精度SAR、NS-SAR ADC。
代表性成果：
其他ADC
研究高速Flash ADC、低功耗SAR ADC、高精度sigma-delta ADC、低功耗时域/相位域ADC等。
代表性成果：
已发表论文
期刊论文
[JSSC 2022]Yuekang Guo, Jing Jin*, Xiaoming Liu, and Jianjun Zhou, “A 60MS/s 5MHz-BW Noise-Shaping SAR ADC with Integrated Input Buffer Achieving 84.2dB-SNDR and 97.3dB-SFDR Using Dynamic Level-Shifting and ISI-Error Correction,” in IEEE Journal of Solid-State Circuits, DOI 10.1109/JSSC.2022.3185501.
[TCAS-I 2022]Y. Guo, J. Jin, X. Liu and J. Zhou, “An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, doi: 10.1109/TCSI.2022.3192465.
[TCAS-II 2021]H. Ghaedrahmati, J. Zhou and R. B. Staszewski, “A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass Σ ADC in 28 nm Using Asynchronous SAR Quantizer,” in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2021.3089831.
[CSSP 2021]M. Hu, J. Jin, Y. Guo, X. Liu and J. Zhou, “A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS,” in Circuits Syst. Signal Process, Jan 2021.
[TCAS-I 2020]Y. Guo, J. Jin, X. Liu and J. Zhou, “An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp.3630-3642, Nov. 2020.
[IET-CDS 2018]R. Guan, J. Xue, C. Yang, J. Jin and J. Zhou, “16-bit 1-MS/s SAR ADC with foreground digital-domain calibration,” in IET Circuits, Devices & Systems, vol. 12, no. 4, pp. 505-513, 7 2018.
[MJ 2018]Rui Guan, Jing Jin, Jianjun Zhou, “A low-cost digital-domain foreground Calibration for high resolution SAR ADCs,” Microelectronics Journal, vol. 73, pp.86-93, Jul. 2018.
[EL 2018]H. Ghaedrahmati and J. Zhou, “160 MS/s 20 MHz bandwidth third-order noise shaping SAR ADC,” in Electronics Letters, vol. 54, no. 3, pp. 128-130, 8 2 2018.
[AICSP 2018]Yuke Zhang, Kamal El-Sankary, and Jianjun Zhou, “A Blind Digital Background Calibration for All-digital VCO-Based ADC,” Analog Integrated Circuits and Signal Processing, Vol 97, Issue 2, pp 387-394, Nov. 2018.
[CJE 2015]K. Wang, C. Fan, et al, “Nonlinearity Calibration for Pipelined ADCs by Splitting Capacitors with Self-Tracking Comparator Thresholds,” in Chinese Journal of Electronics, vol. 24, no. 3, pp. 474-479, 07 2015.
[ELEX 2015]Ke Wang, Chaojie Fan, et al,“A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR,” IEICE Electronics Express, 2015, 12: 20150070.
[ELEX 2014]Fan Chaojie, Wang Ke, et al, Nonlinear inter-stage gain calibration for pipelined ADCs employing double dithering modes, IEICE Electronics Express, 2014, Volume 11, Issue 23, Pages 20140995, Released December 10, 2014
[ELEX 2014]Yuxiao Lu, Chaojie Fan, Lu Sun, Zhe Li, Jianjun Zhou, A fast low power window-opening logic for high speed SAR ADC, IEICE Electronics Express, 2014, Volume 11, Issue 14, Pages 20140454, Released July 25, 2014
[ELEX 2014]Fan Chaojie, Lu Yuxiao, Wang Ke, Zhou Jianjun, Digital nonlinearity calibration for pipelined ADCs using sampling capacitors splitting, IEICE Electronics Express, 2014, Volume 11, Issue 13, Pages 20140442, Released July 10, 2014,
[JOS 2014]LU Yuxiao, SUN Lu, LI Zhe, ZHOU Jianjun, “A single-channel 10-bit 160MS/s SAR ADC in 65nm CMOS,” Journal of Semiconductors, 35(4), pages 045009，Apr. 2014.
[JOS 2013]Wang Ke, Fan Chaojie, Zhou Jianjun, et al(2013). A 14-bit 100-MS/s CMOS pipelined ADC with 113 ENOB. Journal of Semiconductors, 34(8), 5. doi:101088/1674-4926/34/8/085015
会议论文
[MWSCAS 2021]Y. Guo, J. Jin and J. Zhou, “A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC,” 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Lansing, MI, USA, 2021, pp. 18-21.
[MWSCAS 2021]Y. He, Y. Guo, J. Jin and J. Zhou, “A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs,” 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Lansing, MI, USA, 2021, pp. 941-944.
[ISCAS 2021]Y. Guo, J. Jin, X. Liu and J. Zhou, “A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-based Continuous-Time ΔΣ ADC,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-4, doi: 10.1109/ISCAS51556.2021.9401304.
[MWSCAS 2018]H. Ghaedrahmati, J. Zhou and L. Shi, “Gain-boosted Complementary Dynamic Residue Amplifier for a 160 MS/s 61 dB SNDR Noise-Shaping SAR ADC,” 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, ON, Canada, 2018, pp. 141-144.
[MWSCAS 2015]Xuan Li, Shuo Huang, Jianjun Zhou and Xiaoyong Li, “A 12-bit 20-MS/s SAR ADC with improved internal clock generator and SAR controller,” 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, CO, 2015, pp. 1-4.
[ICSICT 2020]Mengying Hu, Yuekang Guo, Jing Jin, “A VCO-Based Continuous Time Delta-sigma ADC with An Alternative Feedforward Scheme VCO, “2020 15th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Kunming, pp. 1-3.
[ASICON 2019]Yifei Wang, Xiaofei Wang, Yuekang Guo and Jing Jin,” A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS, “The IEEE 13th International Conference on ASIC, Oct. 29 – Nov. 1, 2019, Chongqing, China.
[ICSICT 2018]J. Xue, H. Ghaedrahmati and J. Jin, “A 10-bit 160MS/s SAR ADC with Fast-Response Reference Voltage Buffer,” 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Qingdao, 2018, pp. 1-3.
[ICCSS 2018]H. Ghaedrahmati, J. Xue, J. Jin and J. Zhou, “A 1mW 20MHz Bandwidth 9.51-ENOB Dynamic-Amplifier-Based Noise-Shaping SAR ADC,” 2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS), Guangzhou, 2018, pp. 9-12.
[ICCCAS 2018]Y. Yan, H. Xu and J. Jin, “A High-Speed Pipelined-SAR ADC with Resistor-based Self-biasing RAMP,” 2018 10th International Conference on Communications, Circuits and Systems (ICCCAS), Chengdu, China, 2018, pp. 378-382.
[ICCC 2017]A. Fan and J. Jin, “A highly-linearized ring amplifier with gain offset calibration,” 2017 3rd IEEE International Conference on Computer and Communications (ICCC), Chengdu, 2017, pp. 1372-1376.
[ICSICT 2016]Rong-Tao Liao, Rui Guan and Ting-Ting Mo, “A directly triggered asynchronous SAR logic with variable delay unit,” 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Hangzhou, 2016, pp. 912-914.
[ASICON 2015]S. Huang, X. Li and X. Li, “A 14b 1GS/s DAC with SFDR > 80 dBc across the whole nyquist band by mixed total 3-dimesional sort-and-combine and dynamic element matching,” 2015 IEEE 11th International Conference on ASIC (ASICON), Chengdu, 2015, pp. 1-4.
[ICSICT 2014]C. Guo, R. Guan, et al, “A 1-G sample/S 71-dB SFDR CMOS S/H circuit,” 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, 2014, pp. 1-3.
[ASICON 2013]Chaojie Fan, et al, “Digital calibration techniques for interstage gain nonlinearity in pipelined ADCs,” 2013 IEEE 10th International Conference on ASIC, Shenzhen, 2013, pp. 1-4.
[ASICON 2013]Yun Chen, Chaojie Fan and Jianjun Zhou, “Low jitter clock driver for high-performance pipeline ADC,” 2013 IEEE 10th International Conference on ASIC, Shenzhen, 2013, pp. 1-4.
[ASICON 2013]Lu Sun, Yuxiao Lu and Tingting Mo, “A 300MHz 10b time-interleaved pipelined-SAR ADC,” 2013 IEEE 10th International Conference on ASIC, Shenzhen, 2013, pp. 1-4.
[ASICON 2013]Zhe Li, Yuxiao Lu and Tingting Mo, “Calibration for split capacitor DAC in SAR ADC,” 2013 IEEE 10th International Conference on ASIC, Shenzhen, 2013, pp. 1-4.
[ICSICT 2012]T. Tao, C. Fan, et al, “A 1.8V low noise threshold voltage reference generator with temperature and process calibration,” 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Xi’an, 2012, pp. 1-3.
[ICMTMA 2011]Y. Yan, T. Yan, T. Mo, et al, “A 62MHz~316MHz Phase-Locked Loop Based on Ring Oscillator for ADC Clock Generator in 0.18m CMOS,” 2011 Third International Conference on Measuring Technology and Mechatronics Automation, Shangshai, 2011, pp. 6-8.
[ICMTMA 2011]W. Lei, Y. Taotao, M. Tingting and M. Cui, “A 14-b 2MSPS Low Power Sigma-Delta ADC Using Feed-Forward Structure,” 2011 Third International Conference on Measuring Technology and Mechatronics Automation, Shangshai, 2011, pp. 3-5.